(1) Field of the Invention
The present invention relates to a semiconductor device and a method of manufacture thereof, and particularly to a double diffused metal oxide semiconductor (DMOS) transistor that is inexpensive and that consumes a small mount of power.
(2) Description of the Related Art
Along with a decrease in power consumption as well as in cost of motor driver circuits, recent years have seen an increasing use of a technology that employs, as a semiconductor device of a motor driver circuits, a lateral DMOS transistor (hereinafter referred to as “DMOS transistor(s)”) being a power device.
DMOS transistors, which have high-breakdown voltage and can therefore reduce on-resistance, are widely used as a transistor of an output circuit or the like of a motor driver circuit since they are optimum transistors as power devices. FIG. 1 is a circuit diagram showing an example output circuit of a motor driver circuit.
As shown in FIG. 1, an output circuit is comprised of: a first DMOS transistor 403 that is placed between a power line 401 and an output terminal 402; a second DMOS transistor 406 that is placed between the output terminal 402 and a ground line 405; and a control circuit 404 that controls on/off of the first DMOS transistor 403 and second DMOS transistor 406, being connected to gates thereof. In this case, a drain of the first DMOS transistor 403 is connected to the power line 401, and a source and body of the first DMOS transistor 403 are connected to the output terminal 402. Meanwhile, a drain of the second DMOS transistor 406 is connected to the output terminal 402, and a source and body of the second DMOS transistor 406 are connected to the ground line 405.
In order to drive a motor (not illustrated in this figure) that is connected to the output terminal 402, the output circuit with the above structure passes a current for driving the motor to the output terminal 402, by alternately turning on the first DMOS transistor 403 and the second DMOS transistor 406. Meanwhile, in order to stop the motor, the output circuit passes, to the power line 401, a regenerative current that has come from the output terminal 402 by turning off the first DMOS transistor 403 and second DMOS transistor 406, and by operating a parasitic diode of the first DMOS transistor 403 to minimize power consumption. When this is done, the regenerative current does not flow into the ground line 405.
FIGS. 2A to 2C are cross-sectional diagrams for explaining a method of manufacturing the first DMOS transistor 403/second DMOS transistor 406.
First, as shown in FIG. 2A, an N-type buried layer 502 and an N-type epitaxial layer 503 are sequentially formed on a P-type silicon substrate 501. When this is done, the N-type buried layer 502 is formed so that its concentration is higher than that of the N-type epitaxial layer 503. Such N-type buried layer 502 and N-type epitaxial layer 503 serve as a drain 504 of the DMOS transistor.
Next, as shown in FIG. 2B, a gate electrode 505 made of a gate oxide film and polysilicon is formed on the N-type epitaxial layer 503, after which a P-type body layer 506 is formed in the N-type epitaxial layer 503 by self alignment that uses the gate electrode 505 as a mask, and then an N-type source layer 507 is formed in such P-type body layer 506. Then, an N-type drain contact layer 508 is formed on a portion, in the N-type epitaxial layer 503, that is distant from the gate electrode 505. Here, a parasitic diode is formed by the P-type body layer 506 and the N-type epitaxial layer 503.
Next, as shown in FIG. 2C, the P-type body layer 506 and the N-type source layer 507 are connected to the same metal wire, and the N-type drain contact layer 508 is connected to a metal wire. Here, since the P-type silicon substrate 501 is connected to ground, a parasitic PNP transistor is formed in which the P-type body layer 506 serves as an emitter, the drain 504 serves as a base, and the P-type silicon substrate 501 as a collector.
In the first DMOS transistor 403 that is manufactured through the above manufacturing processes, the N-type buried layer 502 of the same conductivity type as that of the N-type epitaxial layer 503 is formed below the N-type epitaxial layer 503. This structure makes it possible to reduce power loss caused by the DMOS transistor since an hfe of the parasitic PNP transistor that operates at a time of passing a regenerative current to the power line 401 is lowered and a current is prevented from flowing into the P-type silicon substrate 501 being the ground. In other words, when a regenerative current is passed to the power line 401, holes being minority carriers are injected from the P-type body layer 506 to the drain 504 and flow into the P-type silicon substrate 501. As a result, a bipolar action occurs and a current is passed. However, existence of the N-type buried layer 502 causes holes to be recombined with each other inside the N-type buried layer 502, as a result of which the hfe of the parasitic PNP transistor becomes small.
Here, a technology related to DMOS transistors used in the above output circuit is disclosed in Japanese Patent No. 3372773 publication. This technology is directed to provide inexpensive DMOS transistors in order to minimize costs of chips. Such object is achieved, as shown in FIG. 3, that is a cross-sectional diagram of a DMOS transistor, by using as the drain of the DMOS transistor an N-type well layer 600 used for a P-channel MOS transistor (not illustrated in this figure) that constitutes a complementary metal oxide semiconductor (CMOS) transistor formed in the same substrate. Stated another way, it is possible to provide an inexpensive DMOS transistor since formation of an N-type buried layer and an N-type epitaxial layer is not required.
Furthermore, Japanese Laid-Open Patent application No. 5-190777 publication discloses a technology related to a transistor having an N-type buried layer. This technology is directed to provide an inexpensive Bi-CMOS device that controls noise generated in a bipolar transistor at a time of switching a CMOS transistor. Such object is achieved, as shown in FIG. 4, that is a cross-sectional diagram of a bipolar transistor, by forming an N-type buried layer 610 in a lower part of the bipolar transistor by performing an ion implantation method.
However, since conventional DMOS transistors having an N-type buried layer require formation, on a P-type silicon substrate, of an N-type buried layer and an N-type epitaxial layer, there occurs a problem in that a number of manufacturing processes increases and therefore cost of DMOS transistors becomes high.
Furthermore, the technology disclosed in Japanese Patent No. 3372773 publication is capable of providing an inexpensive DMOS transistor since a drain of the DMOS transistor is formed only by an N-type well layer of the CMOS transistor. However, since it includes no N-type buried layer, holes are not recombined frequently inside the drain, as a result of which a problem occurs in that an hfe of the parasitic PNP transistor becomes high and therefore power loss caused by the DMOS transistor becomes large.
Moreover, a bipolar transistor having an N-type buried layer disclosed in Japanese Laid-Open Patent application No. 5-190777 publication has a problem in that it cannot be used for the above-described output circuit or the like since no parasitic diode is formed.
In view of the above problems, it is conceivable to employ a method that uses, as structure of a DMOS transistor, structure of a bipolar transistor disclosed in Japanese Laid-Open patent application No. 5-190777 publication, as a method of providing an inexpensive DMOS transistor that has a parasitic diode and that lowers the hfe of the parasitic PNP transistor. However, as shown in FIG. 4, that shows structure of the bipolar transistor, existence of a deep N-type well layer between a base of the bipolar transistor and an N-type buried layer makes a current path at power-on time and the N-type buried layer distant from each other. As a result, on-resistance becomes high, which causes another problem in that power consumption is increased. In other words, during an on state, since a large amount of current flows on a surface of the drain, existence of a deep N-type well layer below the P-type body layer allows only a small amount of current to flow into a low-resistance N-type buried layer and on-resistance becomes high as a result.